Conventional semiconductor devices typically comprise a semiconductor substrate and a plurality of dielectric and conductive layers formed thereon. An integrated circuit contains numerous microelectronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to efficiently provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio, and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of a multilayer substrate on which semiconductor devices are mounted.
Damascene (single damascene) is an interconnection fabrication process in which trenches are formed in an insulating structure and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the trenches of single damascene, the conductive via openings also are formed.
In one type of dual damascene processes, a first mask with the image pattern of the via openings is formed over the insulating structure and the wafer is anisotropically etched in the upper portion of the insulating structure (via etch). After removal of the patterned resist material, a second mask is formed over the insulating structure with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material (trench etch), the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and trenches are filled with metal.
In another type of dual damascene processes, a first mask is formed over the insulating structure with the image pattern of the via openings and the pattern is anisotropically etched in the insulating structure (via etch). After removal of the patterned resist material, a second mask is formed over the insulating structure with the image pattern of the conductive lines in alignment with the via openings and the pattern of the conductive lines is anisotropically etched (trench etch). After the etching is complete, both the vias and trenches are filled with metal.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive trenches and vias with metal at the same time, thereby eliminating process steps. However, deviations from desired dimensions of the trenches may result from variations in the photolithography and etching processes. Such deviations make it difficult to produce semiconductor structures with consistent physical and/or electrical characteristics.
Accordingly, it is desirable to provide a method for controlling the profile of a trench etched into a semiconductor structure. In addition, it is desirable to provide a method for forming a trench during a dual damascene process of a semiconductor structure that provides for consistent feature dimensions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.